Many new emerging applications require the use of ultra-low power consumption solutions inside a chip. This will allow them to be incorporated into devices that operate from a small non-chargeable battery for very long periods without the need to frequently charge the battery. For example, wearable, mobile devices and IoT (Internet of Things) devices may require an ultra-low power design flow.
Sub-threshold technology is a way of operating the CMOS transistors in their weak inversion state where the transistors are never fully turned on. When operating in the sub-threshold region, the transistor state varies between being fully turned off and partially turned on.
Sub-threshold technology is considered to be the most energy-efficient solution for low power applications where area and performance is of secondary importance.
When operating in the sub-threshold region, transistors operate at a lower voltage than their threshold voltage (known as VT) and by such operation the transistor uses less power. During sub-threshold voltage operation, the use of both dynamic power and static power is reduced. Dynamic power is a ratio of the operating voltage by a power of two and static power is a ratio of the operating voltage, therefore reducing the operating voltage of the device to a sub-threshold voltage level will reduce the consumed power dramatically.
One of the major limiting factors for using sub-threshold technology is the very low performance of the transistors at a very low voltage and due to this limitation the usage of sub-threshold technology in commercial chips is very limited.
Various methods and implementations for the sub-threshold technology exist today that focus only on power reduction and not on the optimal way to use this technology for a given power per performance required by a specific application.
In order for this technology to have practical application, a method is required that optimizes power consumption while still meeting the performance requirements for a specific product or application.